Integrated chips are fabricated through a plurality of processing steps (e.g., etching steps, lithography steps, deposition steps, etc.) upon a semiconductor wafer (e.g., a silicon wafer), followed by dicing the semiconductor wafer into separate integrated chips. In order to realize higher integration, simplify packaging processes, or couple circuits or other components, etc., in some cases two or more wafers are bonded together before the dicing step, and circuits are fabricated on both sides of the wafer after thin down. Wafer level bonding is a promising technology for “More than Moore”, where added value is provided to devices by incorporating functionality that does not necessarily scale according to Moore's Law. Debonding is desired in some cases during the wafer level bonding procedure, and can be used for example to separate one wafer from another, and can be used to rework a substrate when alignment is out of spec or particulates that fall onto a wafer cause interface voids, etc.